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ASICS & FPGA Consultants For Networking

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 Local Area Contrast Enhancement with Dynamic Range Compression is available under NDA. Please contact sales.

DESIGN IP

VERIFICATION IP

Image Processing Pipeline

DS3 Generator and Analyzer

Digital Camera Pipeline

E3 Generator and Analyzer

Infiniband 10 80 Gbps Link Layer

DS3 over SONET Generator and Analyzer

Infiniband 10 Gbps Transport Layer

E3 over SONET Generator and Analyzer 

Scene Based Infrared Autofocus

DS3 eVC

STS48 based 1344x1344 VT Cross-Connect

SPI-3 Link Layer eVC

2 x STS12 STS/VT Cross-Connect with 1xSTS12 Add/Drop

SPI-3 PHY Layer eVC

STS1 based 250 msec Delay Compensation

Vitesse VSC 9675

STS48 to 4 x STS 12 Convertor

Intel IXF1002

STS48 to 4 x STS 3 Convertor

 

STS48 to 48 DS3 Mapper/DeMapper

 

STS1 based 250 msec Delay Introduction

 

STM16 to 48 E3 Mapper/DeMapper

 

Double Data Rate DDR Controller

 

 


 


 

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Last modified: January 9, 2015