Tenesix Inc.
ASICS & FPGA Consultants For Networking

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DESIGN IP	VERIFICATION IP
Image Processing Pipeline	DS3 Generator and Analyzer
Infiniband 10 – 80 Gbps Link Layer	E3 Generator and Analyzer
Infiniband 10 Gbps Transport Layer	DS3 over SONET Generator and Analyzer
STS48 based 1344x1344 VT Cross-Connect	E3 over SONET Generator and Analyzer
2 x STS12 STS/VT Cross-Connect with 1xSTS12 Add/Drop	DS3 eVC
STS1 based 250 msec Delay Compensation	SPI-3 Link Layer eVC
STS48 to 4 x STS 12 Convertor	SPI-3 PHY Layer eVC
STS48 to 4 x STS 3 Convertor	Vitesse VSC 9675
STS48 to 48 DS3 Mapper/DeMapper	Intel IXF1002
STS1 based 250 msec Delay Introduction
STM16 to 48 E3 Mapper/DeMapper
Double Data Rate DDR Controller

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Last modified: January 21, 2004